A conventional branch target address cache (BTAC) has a limitation of storing information about only two branch instructions in a given aligned 16-byte piece of instruction data. This design choice was made to improve timing considerations and to reduce power consumption and die size. Allowing three or four branches is significantly more complex than two. Although it is relatively rare to have three or more branches with their initial byte all in the same 16-byte fetch from the instruction cache, the situation does occur and can, therefore, have a negative impact on performance.